1. Field of the Invention
Embodiments of the invention relate generally to non-volatile semiconductor memory devices. More particularly, embodiments of the invention relate to non-volatile semiconductor memory devices in which a plurality of memory sectors are simultaneously erased.
A claim of priority is made to Korean Patent Application No. 10-2006-46181 filed May 23, 2006, the disclosure of which is hereby incorporated by reference in its entirety.
2. Description of Related Art
In conventional non-volatile semiconductor memory devices, erase operations are typically performed on a single memory sector (i.e., a block) or a plurality of memory sectors. A typical erase operation includes an erase procedure and an erase verification procedure. In the erase procedure, a voltage difference is applied between the respective control gates and bulk region(s) of selected memory cells so that charges trapped in the respective floating gates of the selected memory cell are restored to the corresponding bulk region(s). In the erase verification procedure, data is read from the selected memory cells, and then the data is evaluated to determine whether all of the selected memory cells were successfully erased. Selected cells that were not properly erased in the erase procedure will be referred to hereafter as “failed cells”. If the number of failed cells in an erased sector is greater than or equal to a failed cell threshold value, the erase procedure and the erase verification procedure are repeated on that sector.
Erase operations can be performed in multiple different modes. Moreover, sectors are often erased using multiple erase operations of different modes, carried out in succession. For example, in a first mode erase operation, the erase procedure is repeatedly performed with a successively increased bulk voltage. In a second mode erase operation, which is usually performed after the first mode erase operation, the erase procedure is repeatedly performed with the same voltages applied to control gates and the bulk region(s), but for a relatively increased time. Where a first mode erase operation is performed, the lowest bulk voltage for which the number of failed cells in a selected sector falls below the failed cell threshold value is referred to as an “erase pass voltage”. The second mode erase voltage operation is usually performed on the selected sector after the first mode erase operation is performed with the “erase pass voltage” for that sector to erase remaining failed cells. By using the second mode erase operation to erase the remaining failed cells, rather than continuing to increment the bulk voltage, over erasure and non-erasure of memory cells in the selected sector is avoided.
FIG. 1 is a block diagram of a conventional non-volatile semiconductor memory device. Referring to FIG. 1, the conventional non-volatile semiconductor memory device comprises a memory cell array MCARR and associated peripheral circuits. The peripheral circuits include, for example, an erase verifier 10, a bulk voltage generator 20, a word line voltage generator 30, and a bit line voltage generator 40. These peripheral circuits are used to control various operations for storing and retrieving data from memory cell array MCARR.
Memory cell array MCARR comprises “n” memory banks BANK<1:n>, and each of memory banks BANK<1:n> comprises “m” sectors, where the “m” sectors in the i-th memory bank are labeled SEC<i:1> through SEC<i:m>. Each of the sectors comprises a plurality of non-volatile memory cells. The conventional non-volatile semiconductor memory device further comprises “n” sense amplifier blocks SA<1:n> respectively corresponding to the “n” memory banks BANK<1:n>. Sense amplifier blocks SA<1:n> sense and amplify data stored in the sectors of the corresponding memory banks BANK<1:n>.
To select a sector of memory cells for an erase operation, word line voltage generator 30 generates a word line voltage VWL and applies word line voltage VWL to word line(s) of the memory cell in a selected memory sector. In addition, bit line voltage generator 40 generates a bit line voltage VBL and applies bit line voltage VBL to bit line(s) BL of the memory cell in the selected memory sector.
Following an erase operation of one or more sectors of a selected memory bank among memory banks BANK<1:n>, a corresponding one of sense amplifier blocks SA<1:n> senses and amplifies the data stored in the one or more sectors of the selected memory bank, and provides the amplified data to erase verifier 10 through a data line DL. Erase verifier 10 receives and evaluates the data provided through data line DL and detects whether any cells in the one or more sectors of the selected memory bank failed to be erased in the erase operation.
In the non-volatile semiconductor memory device, the erase operation can be performed in such a way that memory sectors arranged in the same row of memory banks BANK<1:n> are simultaneously erased. For example, sectors SEC<1, 1>, SEC<2, 1>, . . . , SEC<n, 1> can be simultaneously erased.
Where multiple memory sectors in the same row of memory banks BANK<1:n> are simultaneously erased using the first mode erase operation, the different sectors may exhibit different “erase pass voltages”. In other words, some of the sectors may be sufficiently erased with a lower bulk voltage than other sectors.
However, in the conventional non-volatile semiconductor memory device illustrated in FIG. 1, bulk voltage generator 20 applies the same bulk voltage VSUB to the bulk regions of all sectors. Unfortunately, where the multiple sectors have different “erase pass voltages”, using the same bulk voltage VSUB for multiple sectors is inefficient and can cause over-erasure, non-erasure, or excessive wear and tear in some sectors.